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ds07-13704-3e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90590/590g series mb90591/f591a/594/594g/f594a/f594g mb90v590a/v590g n n n n description the mb90590/590g series with two full-can* 1 interfaces and flash rom is especially designed for auto- motive and industrial applications. its main features are two on board can interfaces, which conform to v2.0 part a and part b, while supporting a very flexible message buffer scheme and so offering more functions than a normal full can approach. the instruction set of f 2 mc-16lx cpu core inherits an at architecture of the f 2 mc* 2 family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instruc- tions, and enhanced bit manipulation instructions. the microcontroller has a 32-bit accumulator for processing long word data. the mb90590/590g series has peripheral resources of 8/10-bit a/d converters, uart (sci), extended i/o serial interface, 8/16-bit ppg timer, i/o timer (input capture (icu), output compare (ocu)), stepping motor controller, and sound generator. *1: controller area network (can) - license of robert bosch gmbh *2: f 2 mc stands for fujitsu flexible microcontroller. n n n n features ?clock embedded pll clock multiplication circuit operating clock (pll clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 mhz, 4 mhz to 16 mhz). minimum instruction execution time: 62.5 ns (operation at oscillation of 4 mhz, four times the oscillation clock, v cc of 5.0 v) (continued) n n n n pac k ag e 100-pin plastic qfp (fpt-100p-m06)
mb90590/590g series 2 (continued) ? instruction set to optimize controller applications rich data types (bit, byte, word, long word) rich addressing mode (23 types) enhanced signed multiplication/division instruction and reti instruction functions enhanced precision calculation realized by the 32-bit accumulator ? instruction set designed for high level language (c language) and multi-task operations adoption of system stack pointer enhanced pointer indirect instructions barrel shift instructions ? program patch function (for two address pointers) ? enhanced execution speed: 4-byte instruction queue ? enhanced interrupt function: 8 levels, 34 factors ? automatic data transmission function independent of cpu operation extended intelligent i/o service function (ei 2 os): up to 10 channels ? embedded rom size and types mask rom: 256 kbytes/384 kbytes flash rom: 256 kbytes/384 kbytes embedded ram size: 6 kbytes/8 kbytes ?flash rom supports automatic programming, embedded algorithm tm * write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm hard-wired reset vector available in order to point to a fixed boot sector in flash memory erase can be performed on each block block protection with external programming voltage ? low-power consumption (stand-by) mode sleep mode (mode in which cpu operating clock is stopped) stop mode (mode in which oscillation is stopped) cpu intermittent operation mode clock mode hardware stand-by mode ?process 0.5 m m cmos technology ? i/o port general-purpose i/o ports: 78 ports ?timer watchdog timer: 1 channel 8/16-bit ppg timer: 8/16-bit 6 channels 16-bit re-load timer: 2 channels ? 16-bit i/o timer 16-bit free-run timer: 1 channel input capture: 6 channels output compare: 6 channels ? extended i/o serial interface: 1 channel ? uart (3 channels) with full-duplex double buffer (8-bit length) clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used. ? stepping motor controller (4 channels)
mb90590/590g series 3 ? external interrupt circuit (8 channels) a module for starting an extended intelligent i/o service (ei 2 os) and generating an external interrupt which is triggered by an external input. ? delayed interrupt generation module generates an interrupt request for switching tasks. ? 8/10-bit a/d converter (8 channels) 8/10-bit resolution can be selectively used. starting by an external trigger input. ? full-can interfaces: 2 conforming to version 2.0 part a and part b flexible message buffering (mailbox and fifo buffering can be mixed) ? sound generator ? 18-bit time-base counter ? clock timer: 1 channel ? external bus interface: maximum address space 16 mbytes *: embedded algorithm is a trade mark of advanced micro devices inc.
mb90590/590g series 4 n n n n product lineup (continued) features mb90591/594/594g mb90f591a/f594a/f594g mb90v590a/v590g classification mask rom product flash rom product evaluation product rom size 384/256 kbytes 384/256 kbytes boot block hard-wired reset vector none ram size 8/6 kbytes 8/6 kbytes 8 kbytes emulator-specific power supply * 1 ? none cpu functions the number of instructions: 340 instruction bit length: 8 bits, 16 bits instruction length: 1 byte to 7 bytes data bit length: 1 bit, 8 bits, 16 bits minimum execution time: 62.5 ns (at machine clock frequency of 16 mhz) interrupt processing time: 1.5 m s (at machine clock frequency of 16 mhz, minimum value) uart (3 channels) clock synchronized transmission (500 kbps / 1 mbps / 2 mbps) clock asynchronized transmission (4808/5208/9615/10417/19230/38460/62500 /500000 bps at machine clock frequency of 16 mhz) transmission can be performed by bi-directional serial transmission or by master/ slave connection. 8/10-bit a/d converter conversion precision: 8/10-bit can be selectively used. number of inputs: 8 one-shot conversion mode (converts selected channel once only) scan conversion mode (converts two or more successive channels and can program up to 8 channels) continuous conversion mode (converts selected channel continuously) stop conversion mode (converts selected channel and stop operation repeatedly) 8/16-bit ppg timers (6 channels) number of channels: 6 (8/16-bit 6 channels) ppg operation of 8-bit or 16-bit a pulse wave of given intervals and given duty ratios can be output. pulse interval: fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 , 128 m s (at oscillation of 4 mhz, fsys = system clock frequency of 16 mhz, fosc = oscillation clock frequency) 16-bit reload timer number of channels: 2 operation clock frequency: fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys = system clock frequency) supports external event count function 16-bit i/o timer 16-bit output compares number of channels: 6 (8/16-bit 6 channels) pin input factor: a match signal of compare register input captures number of channels: 6 rewriting a register value upon a pin input (rising, falling, or both edges)
mb90590/590g series 5 (continued) *1: it is setting of dip switch s2 when emulation pod (mb2145-507) is used. please refer to the mb2145-507 hardware manual (2.7 emulator-specific power pin) about details. *2: varies with conditions such as the operating frequency. (see section n electrical characteristics.) features mb90591/594/594g mb90f591a/f594a/f594g mb90v590a/v590g can interface number of channels: 2 conforms to can specification version 2.0 part a and b automatic re-transmission in case of error automatic transmission responding to remote frame prioritized 16 message buffers for data and ids supports multiple messages flexible configuration of acceptance filtering: full bit compare / full bit mask / two partial bit masks supports up to 1mbps can bit timing setting: mb90xxx:tseg2 3 rsjw + 2tq mb90xxxg:tseg2 3 rsjw stepping motor controller (4 channels) four high current outputs for each channel synchronized two 8-bit pwms for each channel external interrupt circuit number of inputs: 8 started by a rising edge, a falling edge, an h level input, or an l level input. sound generator 8-bit pwm signal is mixed with tone frequency from 8-bit reload counter pwm frequency: 62.5k, 31.2k, 15.6k, 7.8khz (at system clock = 16mhz) tone frequency: pwm frequency / 2 / (reload value + 1) extended i/o serial interface clock synchronized transmission (31.25k/62.5k/125k/500k/1mbps at machine clock frequency of 16 mhz) lsb first/msb first clock timer directly operates with the system clock read/write accessible second/minute/hour registers watchdog timer reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 mhz, minimum value) flash memory supports automatic programming, embedded algorithm tm and write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm hard-wired reset vector available in order to point to a fixed boot sector in flash memory boot block configuration erase can be performed on each block block protection with external programming voltage flash writer from minato electronics inc. low-power consumption (stand-by) mode sleep/stop/cpu intermittent operation/clock timer/hardware stand-by process cmos power supply voltage for operation* 2 5 v 10 % (mb90v590a , mb90f594a , mb90594 , mb90v590g, mb90f594g, mb90594g) 5 v 5 % (mb90f591a, mb90591) package qfp-100 pga-256
mb90590/590g series 6 n n n n pin assignment 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 vss p17/sga p16/sgo p15/tx1 p14/rx1 p13/out5 p12/out4 p11/out3 p07/out1 p06/out0 p05/in5 p04/in4 p03/in3 p02/in2 p01/in1 p00/in0 vcc x1 x0 p10/out2 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 2 3 4 5 6 7 9 8 md1 md0 p57/tot/wot p56/tin p67/an7 p66/an6 p65/an5 p64/an4 vss p63/an3 p62/an2 p61/an1 p60/an0 avss avrl avrh avcc p55/ppg5/adtg p54/ppg4 p53/ppg3 p95/int3 p94/int2 p93/int1 rst p92/int0 p91/rx0 p90/tx0 dv ss p87/pwm2m3 p86/pwm2p3 p85/pwm1m3 p84/pwm1p3 dv cc p83/pwm2m2 p82/pwm2p2 p81/pwm1m2 p80/pwm1p2 dv ss p77/pwm2m1 p76/pwm2p1 p75/pwm1m1 p74/pwm1p1 dv cc p73/pwm2m0 p72/pwm2p0 p71/pwm1m0 p70/pwm1p0 dv ss hst md2 p20 p21 p22 p23 p24/int4 p25/int5 p26/int6 p27/int7 p30 p31 p52/ppg2 p51/ppg1 p50/ppg0 c p47/sot3 p46/sck3 p45/scin3 vcc p44/sin2 p43/sck2 p42/sot2 p41/sot1 p40/sck1 p37/sin1 p36/sin0 p35/sck0 p34/sot0 p33 p32 vss (top view) (fpt-100p-m06)
mb90590/590g series 7 n n n n pin description (continued) no. pin name circuit type function 82 x0 a oscillator pin 83 x1 77 rst b reset input 52 hst c hardware standby input 85 to 90 p00 to p05 d general purpose io in0 to in5 inputs for the input captures 91 to 96 p06 to p07 p10 to p13 d general purpose io out0 to out5 outputs for the output compares. to enable the signal outputs, the corresponding bits of the port direc- tion registers should be set to 1. 97 p14 d general purpose io rx1 rx input for can interface 1 98 p15 d general purpose io tx1 tx output for can interface 1. to enable the signal output, the corresponding bit of the port direction register should be set to 1. 99 p16 d general purpose io sgo sgo output for the sound generator. to enable the signal output, the corresponding bit of the port direction register should be set to 1. 100 p17 d general purpose io sga sga output for the sound generator. to enable the signal output, the corresponding bit of the port direction register should be set to 1. 1 to 4 p20 to p23 d general purpose io 5 to 8 p24 to p27 d general purpose io int4 to int7 external interrupt input for int4 to int7 9 to 10 p30 to p31 d general purpose io 12 to 13 p32 to p33 d general purpose io 14 p34 d general purpose io sot0 sot output for uart 0. to enable the signal output, the corresponding bit of the port direction register should be set to 1. 15 p35 d general purpose io sck0 sck input/output for uart 0. to enable the signal output, the corresponding bit of the port direction register should be set to 1.
mb90590/590g series 8 (continued) no. pin name circuit type function 16 p36 d general purpose io sin0 sin input for uart 0 17 p37 d general purpose io sin1 sin input for uart 1 18 p40 d general purpose io sck1 sck input/output for uart 1 19 p41 d general purpose io sot1 sot output for uart 1 20 p42 d general purpose io sot2 sot output for uart 2 21 p43 d general purpose io sck2 sck input/output for uart 2 22 p44 d general purpose io sin2 sin input for uart 2 24 p45 d general purpose io sin3 sin input for the serial io 25 p46 d general purpose io sck3 sck input/output for the serial io 26 p47 d general purpose io sot3 sot output for the serial io 28 to 33 p50 to p55 d general purpose io ppg0 to ppg5, adtg outputs for the programmable pulse generators. pin number 33 is also shared with adtg input for the external trigger of the a/d converter. 38 to 41 p60 to p63 e general purpose io an0 to an3 inputs for the a/d converter 43 to 46 p64 to p67 e general purpose io an4 to an7 inputs for the a/d converter 47 p56 d general purpose io tin tin input for the 16-bit reload timers 48 p57 d general purpose io tot/wot tot output for the 16-bit reload timers and wot output for the watch timer. only one of three output enable flags in these periph- eral blocks can be set at a time. otherwise the output signal has no meaning.
mb90590/590g series 9 (continued) no. pin name circuit type function 54 to 57 p70 to p73 f general purpose io pwm1p0 pwm1m0 pwm2p0 pwm2m0 output for stepping motor controller channel 0. 59 to 62 p74 to p77 f general purpose io pwm1p1 pwm1m1 pwm2p1 pwm2m1 output for stepping motor controller channel 1. 64 to 67 p80 to p83 f general purpose io pwm1p2 pwm1m2 pwm2p2 pwm2m2 output for stepping motor controller channel 2. 69 to 72 p84 to p87 f general purpose io pwm1p3 pwm1m3 pwm2p3 pwm2m3 output for stepping motor controller channel 3. 74 p90 d general purpose io tx0 tx output for can interface 0 75 p91 d general purpose io rx0 rx input for can interface 0 76 p92 d general purpose io int0 external interrupt input for int0 78 p93 d general purpose io int1 external interrupt input for int1 79 p94 d general purpose io int2 external interrupt input for int2 80 p95 d general purpose io int3 external interrupt input for int3 58, 68 dv cc ? dedicated power supply pins for the high current output buffers (pin no. 54 to 72) 53, 63, 73 dv ss ? dedicated ground pins for the high current output buffers (pin no. 54 to 72) 34 av cc power supply power supply for analog circuit pin when turning this power supply on or off, always be sure to first apply electric potential equal to or greater than av cc to v cc . 37 av ss power supply ground level for analog circuit
mb90590/590g series 10 (continued) no. pin name circuit type function 35 avrh power supply reference voltage input pin for analog circuit when turning this power supply on or off, always be sure to first apply electric potential equal to or greater than avrh to av cc . 36 avrl power supply reference voltage input pin for analog circuit 49, 50 md0, md1 c operating mode selection input pins connect directly to v cc or v ss . 51 md2 g operating mode selection input pin connect directly to v cc or v ss . 27 c ? this is the power supply stabilization capacitor pin. it should be con- nected externally to an 0.1 m f ceramic capacitor. 23, 84 v cc power supply power supply (5.0 v) input pin for digital circuit 11,42,81 v ss power supply power supply (gnd) input pin for digital circuit
mb90590/590g series 11 n n n n i/o circuit type (continued) circuit type circuit remarks a ? oscillation feedback resistor: 1 m w approx. b ? hysteresis input with pull-up resistor: 50 k w approx. c ? hysteresis input d ?cmos output ? hysteresis input x1 x0 standby control signal hys r r hys r hys v cc p-ch n-ch r
mb90590/590g series 12 circuit type circuit remarks e ?cmos output ? hysteresis input ? analog input f ? cmos high current output ? hysteresis input g ? hysteresis input with pull-down resistor: 50 k w approx. ? flash version does not have pull-down re- sistor. analog input hys p-ch n-ch r vcc hys high current p-ch n-ch r hys r r
mb90590/590g series 13 n n n n handling devices (1)preventing latch-up cmos ic chips may suffer latch-up under the following conditions: ? a voltage higher than vcc or lower than vss is applied to an input or output pin. ? a voltage higher than the rated voltage is applied between vcc and vss. ? the avcc power supply is applied before the vcc voltage. latch-up may increase the power supply current drastically, causing thermal damage to the device. for the same reason, also be careful not to let the analog power-supply voltage (av cc , avrh, dv cc ) exceed the digital power-supply voltage. (2)treatment of unused pins leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. therefor they must be pulled up or pulled down through resistors. in this case those resistors should be more than 2 k w . unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. (3)using external clock to use external clock, drive x0 pin only and leave x1 pin unconnected. below is a diagram of how to use external clock. using external clock x0 x1 mb90590/590g series
mb90590/590g series 14 (4)power supply pins (vcc/vss) in products with multiple v cc or v ss pins, pins with the same potential are internally connected in the device to avoid abnormal operations including latch-up. however, you must connect the pins to an external power and a ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. make sure to connect v cc and v ss pins via lowest impedance to power lines. it is recommended to provide a bypass capacitor of around 0.1 m f between v cc and v ss pin near the device. (5) pull-up/down resistors the mb90590/590g series does not support internal pull-up/down resistors. use external components where needed. (6) crystal oscillator circuit noises around x0 or x1 pins may cause abnormal operations. make sure to provide bypass capacitors via the shortest distances from x0, x1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure that lines of oscillation circuits do not cross the lines of other circuits. a printed circuit board artwork surrounding the x0 and x1 pins with a ground area for stabilizing the operation is highly recommended. (7) turning-on sequence of power supply to a/d converter and analog inputs make sure to turn on the a/d converter power supply (av cc , avrh, avrl) and analog inputs (an0 to an7) after turning-on the digital power supply (v cc ). turn-off the digital power after turning off the a/d converter supply and analog inputs. in this case, make sure that the voltage does not exceed avrh or av cc (turning on/off the analog and digital power supplies simulta- neously is acceptable). (8) connection of unused pins of a/d converter connect unused pins of a/d converter to av cc = v cc , av ss = avrh = v ss . vcc vss vss vcc vss vcc mb90590/590g series vcc vss vcc vss
mb90590/590g series 15 (9) n.c. pin the n.c. (internally connected) pin must be opened for use. (10) notes on energization to prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 m s or more (0.2 v to 2.7 v). (11) indeterminate outputs from ports 0 and 1 during oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the outputs from ports 0 and 1 become following state. ?if rst pin is h, the outputs become indeterminate. ?if rst pin is l, the outputs become high-impedance. pay attention to the port output timing shown as follow. oscillation setting time *2 power-on reset *1 vcc (power-supply pin) ponr (power-on reset) signal rst (external asynchronous reset) signal rst (internal reset) signal oscillation clock signal ka (internal operation clock a) signal kb (internal operation clock b) signal port (port output) signal period of indeterminated *1:power-on reset time: period of clock frequency 2 17 (clock frequency of 16 mhz: 8.19 ms) *2:oscillation setting time: period of clock frequency 2 18 (clock frequency of 16 mhz: 16.38ms) rst pin is h oscillation setting time *2 power-on reset *1 vcc (power-supply pin) ponr (power-on reset) signal rst (external asynchronous reset) signal rst (internal reset) signal oscillation clock signal ka (internal operation clock a) signal kb (internal operation clock b) signal port (port output) signal high-impedance *1:power-on reset time: period of clock frequency 2 17 (clock frequency of 16 mhz: 8.19 ms) *2:oscillation setting time: period of clock frequency 2 18 (clock frequency of 16 mhz: 16.38ms) rst pin is l
mb90590/590g series 16 (12) initialization the device contains internal registers which are initialized only by a power-on reset. to initialize these registers, please turn on the power again. (13) directions of div a, ri and divw a, rwi instructions in the signed multiplication and division instructions (div a, ri and divw a, rwi), the value of the corre- sponding bank register (dtb, adb, usb, ssb) is set in 00 h . if the values of the corresponding bank registers (dtb,adb,usb,ssb) are set to other than 00 h , the remainder by the execution result of the instruction is not stored in the register of the instruction operand. (14) using realos the use of ei 2 os is not possible with the realos real time operating system.
mb90590/590g series 17 n n n n block diagram ram 6/8 k rom/flash uart 3ch prescaler 3 watch 10-bit adc 8ch sound generator 16-bit clock controller 16-bit input capture 6ch 16-bit output compare 4ch can 2ch external interrupt 8/16-bit ppg 6ch f 2 mc-16lx cpu f 2 mc-16 bus x0,x1 rst hst sot0 to sot2 sck0 to sck2 sin0 to sin2 avcc avss an0 to an7 avrh avrl adtg sgo sga in0 to in5 out0 to out5 ppg0 to ppg5 rx0, rx1 tx0, tx1 int0 to int7 serial i/o prescaler sot3 sck3 sin3 smc 4ch pwm1m0 to pwm1m3 pwm1p0 to pwm1p3 pwm2m0 to pwm2m3 pwm2p0 to pwm2p3 dvcc dvss 256 k/384 k 16-bit reload tin tot/wot timer 2ch timer io timer circuit 8ch
mb90590/590g series 18 n n n n memory space the memory space of the mb90590/590g series is shown below memory space map note: the rom data of bank ff is reflected in the upper address of bank 00, realizing effective use of the c compiler small model. the lower 16-bit of bank ff and the lower 16-bit of bank 00 are assigned to the same address, enabling reference of the table on the rom without stating far. for example, if an attempt has been made to access 00c000 h , the contents of the rom at ffc000 h are accessed. since the rom area of the ff bank exceeds 48 kbytes, the whole area cannot be reflected in the image for the 00 bank. the rom data at ff4000 h to ffffff h looks, therefore, as if it were the image for 004000 h to 00ffff h . thus, it is recommended that the rom data table be stored in the area of ff4000 h to ffffff h . mb90v590a/v590g mb90594/f594a/ 594g/f594g mb90591/f591a ffffff h ff0000 h rom (ff bank) ffffff h ff0000 h rom (ff bank) ffffff h ff0000 h rom (ff bank) feffff h fe0000 h rom (fe bank) feffff h fe0000 h rom (fe bank) feffff h fe0000 h rom (fe bank) fdffff h fd0000 h rom (fd bank) fdffff h fd0000 h rom (fd bank) fdffff h fd0000 h rom (fd bank) fcffff h fc0000 h rom (fc bank) fcffff h fc0000 h rom (fc bank) fcffff h fc0000 h fbffff h fb0000 h rom (fb bank) fbffff h fb0000 h rom (fb bank) faffff h fa0000 h rom (fa bank) faffff h fa0000 h rom (fa bank) f9ffff h f90000 h rom (f9 bank) f9ffff h f90000 h rom (f9 bank) 00ffff h 004000 h rom (image of ff bank) 00ffff h 004000 h rom (image of ff bank) 00ffff h 004000 h rom (image of ff bank) 0028ff h 002100 h ram 2k 0028ff h 002100 h ram 2k 0020ff h 0020ff h 001fff h 001900 h peripheral 001fff h 001900 h peripheral 001fff h 001900 h peripheral 0018ff h 000100 h ram 6k 0018ff h 000100 h ram 6k 0018ff h 000100 h ram 6k 0000bf h 000000 h peripheral 0000bf h 000000 h peripheral 0000bf h 000000 h peripheral
mb90590/590g series 19 n n n n i/o map (continued) address register abbreviation access peripheral initial value 00 h port 0 data register pdr0 r/w port 0 xxxxxxxx b 01 h port 1 data register pdr1 r/w port 1 xxxxxxxx b 02 h port 2 data register pdr2 r/w port 2 xxxxxxxx b 03 h port 3 data register pdr3 r/w port 3 xxxxxxxx b 04 h port 4 data register pdr4 r/w port 4 xxxxxxxx b 05 h port 5 data register pdr5 r/w port 5 xxxxxxxx b 06 h port 6 data register pdr6 r/w port 6 xxxxxxxx b 07 h port 7 data register pdr7 r/w port 7 xxxxxxxx b 08 h port 8 data register pdr8 r/w port 8 xxxxxxxx b 09 h port 9 data register pdr9 r/w port 9 _ _ xxxxxx b 0a h to 0f h reserved 10 h port 0 direction register ddr0 r/w port 0 0 0 0 0 0 0 0 0 b 11 h port 1 direction register ddr1 r/w port 1 0 0 0 0 0 0 0 0 b 12 h port 2 direction register ddr2 r/w port 2 0 0 0 0 0 0 0 0 b 13 h port 3 direction register ddr3 r/w port 3 0 0 0 0 0 0 0 0 b 14 h port 4 direction register ddr4 r/w port 4 0 0 0 0 0 0 0 0 b 15 h port 5 direction register ddr5 r/w port 5 0 0 0 0 0 0 0 0 b 16 h port 6 direction register ddr6 r/w port 6 0 0 0 0 0 0 0 0 b 17 h port 7 direction register ddr7 r/w port 7 0 0 0 0 0 0 0 0 b 18 h port 8 direction register ddr8 r/w port 8 0 0 0 0 0 0 0 0 b 19 h port 9 direction register ddr9 r/w port 9 _ _ 0 0 0 0 0 0 b 1a h reserved 1b h analog input enable register ader r/w port 6, a/d 1 1 1 1 1 1 1 1 b 1c h to 1f h reserved 20 h serial mode control register 0 umc0 r/w uart0 0 0 0 0 0 1 0 0 b 21 h serial status register 0 usr0 r/w 0 0 0 1 0 0 0 0 b 22 h serial input/output data register 0 uidr0/ uodr0 r/w xxxxxxxx b 23 h rate and data register 0 urd0 r/w 0 0 0 0 0 0 0x b 24 h serial mode control register 1 umc1 r/w uart1 0 0 0 0 0 1 0 0 b 25 h serial status register 1 usr1 r/w 0 0 0 1 0 0 0 0 b 26 h serial input/output data register 1 uidr1/ uodr1 r/w xxxxxxxx b 27 h rate and data register 1 urd1 r/w 0 0 0 0 0 0 0x b
mb90590/590g series 20 (continued) address register abbreviation access peripheral initial value 28 h serial mode control register 2 umc2 r/w uart2 0 0 0 0 0 1 0 0 b 29 h serial status register 2 usr2 r/w 0 0 0 1 0 0 0 0 b 2a h serial input/output data register 2 uidr2/ uodr2 r/w xxxxxxxx b 2b h rate and data register 2 urd2 r/w 0 0 0 0 0 0 0x b 2c h serial mode control register (low-order) smcs r/w serial io _ _ _ _0 0 0 0 b 2d h serial mode control register (high-order) smcs r/w 0 0 0 0 0 0 1 0 b 2e h serial data register sdr r/w xxxxxxxx b 2f h edge selector register ses r/w _ _ _ _ _ _ _0 b 30 h external interrupt enable register enir r/w external interrupt 0 0 0 0 0 0 0 0 b 31 h external interrupt request register eirr r/w xxxxxxxx b 32 h external interrupt level register elvr r/w 0 0 0 0 0 0 0 0 b 33 h external interrupt level register elvr r/w 0 0 0 0 0 0 0 0 b 34 h a/d control status register 0 adcs0 r/w a/d converter 0 0 0 0 0 0 0 0 b 35 h a/d control status register 1 adcs1 r/w 0 0 0 0 0 0 0 0 b 36 h a/d data register 0 adcr0 r xxxxxxxx b 37 h a/d data register 1 adcr1 r/w 0 0 0 0 1 0 xx b 38 h ppg0 operation mode control register ppgc0 r/w 16-bit programmable pulse generator 0/1 0 _ 0 0 0 _ _ 1 b 39 h ppg1 operation mode control register ppgc1 r/w 0 _ 0 0 0 0 0 1 b 3a h ppg0,1 output pin control register ppg01 r/w 0 0 0 0 0 0 0 0 b 3b h reserved 3c h ppg2 operation mode control register ppgc2 r/w 16-bit programmable pulse generator 2/3 0 _ 0 0 0 _ _1 b 3d h ppg3 operation mode control register ppgc3 r/w 0 _ 0 0 0 0 0 1 b 3e h ppg2,3 output pin control register ppg23 r/w 0 0 0 0 0 0 0 0 b 3f h reserved 40 h ppg4 operation mode control register ppgc4 r/w 16-bit programmable pulse generator 4/5 0 _ 0 0 0 _ _ 1 b 41 h ppg5 operation mode control register ppgc5 r/w 0 _ 0 0 0 0 0 1 b 42 h ppg4,5 output pin control register ppg45 r/w 0 0 0 0 0 0 0 0 b 43 h reserved 44 h ppg6 operation mode control register ppgc6 r/w 16-bit programmable pulse generator 6/7 0 _ 0 0 0 _ _ 1 b 45 h ppg7 operation mode control register ppgc7 r/w 0 _ 0 0 0 0 0 1 b 46 h ppg6,7 output pin control register ppg67 r/w 0 0 0 0 0 0 0 0 b 47 h reserved
mb90590/590g series 21 (continued) address register abbreviation access peripheral initial value 48 h ppg8 operation mode control register ppgc8 r/w 16-bit programmable pulse generator 8/9 0 _ 0 0 0 _ _ 1 b 49 h ppg9 operation mode control register ppgc9 r/w 0 _ 0 0 0 0 0 1 b 4a h ppg8,9 output pin control register ppg89 r/w 0 0 0 0 0 0 0 0 b 4b h reserved 4c h ppga operation mode control register ppgca r/w 16-bit programmable pulse generator a/b 0 _ 0 0 0 _ _ 1 b 4d h ppgb operation mode control register ppgcb r/w 0 _ 0 0 0 0 0 1 b 4e h ppga,b output pin control register ppgab r/w 0 0 0 0 0 0 0 0 b 4f h reserved 50 h timer control status register 0 (low-order) tmcsr0 r/w 16-bit reload timer 0 0 0 0 0 0 0 0 0 b 51 h timer control status register 0 (high-order) tmcsr0 r/w _ _ _ _ 0 0 0 0 b 52 h timer control status register 1 (low-order) tmcsr1 r/w 16-bit reload timer 1 0 0 0 0 0 0 0 0 b 53 h timer control status register 1 (high-order) tmcsr1 r/w _ _ _ _ 0 0 0 0 b 54 h input capture control status register 0/1 ics01 r/w input capture 0/1 0 0 0 0 0 0 0 0 b 55 h input capture control status register 2/3 ics23 r/w input capture 2/3 0 0 0 0 0 0 0 0 b 56 h input capture control status register 4/5 ics45 r/w input capture 4/5 0 0 0 0 0 0 0 0 b 57 h reserved 58 h output compare control status register 0 ocs0 r/w output compare 0/1 0 0 0 0 _ _ 0 0 b 59 h output compare control status register 1 ocs1 r/w _ _ _0 0 0 0 0 b 5a h output compare control status register 2 ocs2 r/w output compare 2/3 0 0 0 0 _ _ 0 0 b 5b h output compare control status register 3 ocs3 r/w _ _ _ 0 0 0 0 0 b 5c h output compare control status register 4 ocs4 r/w output compare 4/5 0 0 0 0 _ _ 0 0 b 5d h output compare control status register 5 ocs5 r/w _ _ _ 0 0 0 0 0 b 5e h sound control register (low-order) sgcr r/w sound generator 0 0 0 0 0 0 0 0 b 5f h sound control register (high-order) sgcr r/w 0 _ _ _ _ _ _ 0 b
mb90590/590g series 22 (continued) address register abbreviation access peripheral initial value 60 h watch timer control register (low-order) wtcr r/w watch timer 0 0 0 _ _ 0 0 0 b 61 h watch timer control register (high-order) wtcr r/w 0 0 0 0 0 0 0 0 b 62 h pwm control register 0 pwc0 r/w stepping motor controller 0 0 0 0 0 0 _ _ 0 b 63 h reserved 64 h pwm control register 1 pwc1 r/w stepping motor controller 1 0 0 0 0 0 _ _ 0 b 65 h reserved 66 h pwm control register 2 pwc2 r/w stepping motor controller 2 0 0 0 0 0 _ _ 0 b 67 h reserved 68 h pwm control register 3 pwc3 r/w stepping motor controller 3 0 0 0 0 0 _ _ 0 b 69 h to 6c h reserved 6d h serial io prescaler register cdcr r/w prescaler (serial io) 0 xxx 1 1 1 1 b 6e h timer control status register tccs r/w i/o timer 0 0 0 0 0 0 0 0 b 6f h rom mirror function select register romm w rom mirror xxxxxxx1 b 70 h to 8f h reserved for can interface 0/1. refer to section about can controller 90 h to 9d h reserved 9e h program address detection control status register pacsr r/w address match detection function 0 0 0 0 0 0 0 0 b 9f h delayed interrupt/release register dirr r/w delayed interrupt _ _ _ _ _ _ _ 0 b a0 h low power mode control register lpmcr r/w low power controller 0 0 0 1 1 0 0 0 b a1 h clock selection register ckscr r/w low power controller 1 1 1 1 1 1 0 0 b a2 h to a7 h reserved a8 h watchdog timer control register wdtc r/w watchdog timer xxxxx 1 1 1 b a9 h time base timer control register tbtc r/w time base timer 1 - - 0 0 1 0 0 b aa h to ad h reserved ae h flash memory control status register (flash product only. otherwise reserved) fmcs r/w flash memory 0 0 0 x 0 0 0 0 b af h reserved
mb90590/590g series 23 (continued) address register abbreviation access peripheral initial value b0 h interrupt control register 00 icr00 r/w interrupt controller 0 0 0 0 0 1 1 1 b b1 h interrupt control register 01 icr01 r/w 0 0 0 0 0 1 1 1 b b2 h interrupt control register 02 icr02 r/w 0 0 0 0 0 1 1 1 b b3 h interrupt control register 03 icr03 r/w 0 0 0 0 0 1 1 1 b b4 h interrupt control register 04 icr04 r/w 0 0 0 0 0 1 1 1 b b5 h interrupt control register 05 icr05 r/w 0 0 0 0 0 1 1 1 b b6 h interrupt control register 06 icr06 r/w 0 0 0 0 0 1 1 1 b b7 h interrupt control register 07 icr07 r/w 0 0 0 0 0 1 1 1 b b8 h interrupt control register 08 icr08 r/w 0 0 0 0 0 1 1 1 b b9 h interrupt control register 09 icr09 r/w 0 0 0 0 0 1 1 1 b ba h interrupt control register 10 icr10 r/w 0 0 0 0 0 1 1 1 b bb h interrupt control register 11 icr11 r/w 0 0 0 0 0 1 1 1 b bc h interrupt control register 12 icr12 r/w 0 0 0 0 0 1 1 1 b bd h interrupt control register 13 icr13 r/w 0 0 0 0 0 1 1 1 b be h interrupt control register 14 icr14 r/w 0 0 0 0 0 1 1 1 b bf h interrupt control register 15 icr15 r/w 0 0 0 0 0 1 1 1 b c0 h to ff h reserved 1900 h reload l register prll0 r/w 16-bit programmable pulse generator 0/1 xxxxxxxx b 1901 h reload h register prlh0 r/w xxxxxxxx b 1902 h reload l register prll1 r/w xxxxxxxx b 1903 h reload h register prlh1 r/w xxxxxxxx b 1904 h reload l register prll2 r/w 16-bit programmable pulse generator 2/3 xxxxxxxx b 1905 h reload h register prlh2 r/w xxxxxxxx b 1906 h reload l register prll3 r/w xxxxxxxx b 1907 h reload h register prlh3 r/w xxxxxxxx b 1908 h reload l register prll4 r/w 16-bit programmable pulse generator 4/5 xxxxxxxx b 1909 h reload h register prlh4 r/w xxxxxxxx b 190a h reload l register prll5 r/w xxxxxxxx b 190b h reload h register prlh5 r/w xxxxxxxx b 190c h reload l register prll6 r/w 16-bit programmable pulse generator 6/7 xxxxxxxx b 190d h reload h register prlh6 r/w xxxxxxxx b 190e h reload l register prll7 r/w xxxxxxxx b 190f h reload h register prlh7 r/w xxxxxxxx b
mb90590/590g series 24 (continued) address register abbreviation access peripheral initial value 1910 h reload l register prll8 r/w 16-bit programmable pulse generator 8/9 xxxxxxxx b 1911 h reload h register prlh8 r/w xxxxxxxx b 1912 h reload l register prll9 r/w xxxxxxxx b 1913 h reload h register prlh9 r/w xxxxxxxx b 1914 h reload l register prlla r/w 16-bit programmable pulse generator a/b xxxxxxxx b 1915 h reload h register prlha r/w xxxxxxxx b 1916 h reload l register prllb r/w xxxxxxxx b 1917 h reload h register prlhb r/w xxxxxxxx b 1918 h to 191f h reserved 1920 h input capture register 0 (low-order) ipcp0 r input capture 0/1 xxxxxxxx b 1921 h input capture register 0 (high-order) ipcp0 r xxxxxxxx b 1922 h input capture register 1 (low-order) ipcp1 r xxxxxxxx b 1923 h input capture register 1 (high-order) ipcp1 r xxxxxxxx b 1924 h input capture register 2 (low-order) ipcp2 r input capture 2/3 xxxxxxxx b 1925 h input capture register 2 (high-order) ipcp2 r xxxxxxxx b 1926 h input capture register 3 (low-order) ipcp3 r xxxxxxxx b 1927 h input capture register 3 (high-order) ipcp3 r xxxxxxxx b 1928 h input capture register 4 (low-order) ipcp4 r input capture 4/5 xxxxxxxx b 1929 h input capture register 4 (high-order) ipcp4 r xxxxxxxx b 192a h input capture register 5 (low-order) ipcp5 r xxxxxxxx b 192b h input capture register 5 (high-order) ipcp5 r xxxxxxxx b 192c h to 192f h reserved
mb90590/590g series 25 (continued) address register abbreviation access peripheral initial value 1930 h output compare register 0 (low-order) occp0 r/w output compare 0/1 xxxxxxxx b 1931 h output compare register 0 (high-order) occp0 r/w xxxxxxxx b 1932 h output compare register 1 (low-order) occp1 r/w xxxxxxxx b 1933 h output compare register 1 (high-order) occp1 r/w xxxxxxxx b 1934 h output compare register 2 (low-order) occp2 r/w output compare 2/3 xxxxxxxx b 1935 h output compare register 2 (high-order) occp2 r/w xxxxxxxx b 1936 h output compare register 3 (low-order) occp3 r/w xxxxxxxx b 1937 h output compare register 3 (high-order) occp3 r/w xxxxxxxx b 1938 h output compare register 4 (low-order) occp4 r/w output compare 4/5 xxxxxxxx b 1939 h output compare register 4 (high-order) occp4 r/w xxxxxxxx b 193a h output compare register 5 (low-order) occp5 r/w xxxxxxxx b 193b h output compare register 5 (high-order) occp5 r/w xxxxxxxx b 193c h to 193f h reserved 1940 h timer 0/reload register 0 (low-order) tmr0/ tmrlr0 r/w 16-bit reload timer 0 xxxxxxxx b 1941 h timer 0/reload register 0 (high-order) tmr0/ tmrlr0 r/w xxxxxxxx b 1942 h timer 1/reload register 1 (low-order) tmr1/ tmrlr1 r/w 16-bit reload timer 1 xxxxxxxx b 1943 h timer 1/reload register 1 (high-order) tmr1/ tmrlr1 r/w xxxxxxxx b 1944 h timer data register (low-order) tcdt r/w io timer 0 0 0 0 0 0 0 0 b 1945 h timer data register (high-order) tcdt r/w 0 0 0 0 0 0 0 0 b 1946 h frequency data register sgfr r/w sound generator xxxxxxxx b 1947 h amplitude data register sgar r/w xxxxxxxx b 1948 h decrement grade register sgdr r/w xxxxxxxx b 1949 h tone count register sgtr r/w xxxxxxxx b
mb90590/590g series 26 (continued) address register abbreviation access peripheral initial value 194a h sub-second data register (low-order) wtbr r/w watch timer xxxxxxxx b 194b h sub-second data register (middle-order) wtbr r/w xxxxxxxx b 194c h sub-second data register (high-order) wtbr r/w _ _ _ xxxxx b 194d h second data register wtsr r/w _ _ 0 0 0 0 0 0 b 194e h minute data register wtmr r/w watch timer _ _ 0 0 0 0 0 0 b 194f h hour data register wthr r/w _ _ _ 0 0 0 0 0 b 1950 h pwm1 compare register 0 pwc10 r/w stepping motor controller 0 xxxxxxxx b 1951 h pwm2 compare register 0 pwc20 r/w xxxxxxxx b 1952 h pwm1 select register 0 pws10 r/w _ _ 0 0 0 0 0 0 b 1953 h pwm2 select register 0 pws20 r/w _ 0 0 0 0 0 0 0 b 1954 h pwm1 compare register 1 pwc11 r/w stepping motor controller 1 xxxxxxxx b 1955 h pwm2 compare register 1 pwc21 r/w xxxxxxxx b 1956 h pwm1 select register 1 pws11 r/w _ _ 0 0 0 0 0 0 b 1957 h pwm2 select register 1 pws21 r/w _ 0 0 0 0 0 0 0 b 1958 h pwm1 compare register 2 pwc12 r/w stepping motor controller 2 xxxxxxxx b 1959 h pwm2 compare register 2 pwc22 r/w xxxxxxxx b 195a h pwm1 select register 2 pws12 r/w _ _ 0 0 0 0 0 0 b 195b h pwm2 select register 2 pws22 r/w _ 0 0 0 0 0 0 0 b 195c h pwm1 compare register 3 pwc13 r/w stepping motor controller 3 xxxxxxxx b 195d h pwm2 compare register 3 pwc23 r/w xxxxxxxx b 195e h pwm1 select register 3 pws13 r/w _ _ 0 0 0 0 0 0 b 195f h pwm2 select register 3 pws23 r/w _0 0 0 0 0 0 0 b 1960 h to 19ff h reserved 1a00 h to 1aff h reserved for can interface 0. refer to section about can controller 1b00 h to 1bff h reserved for can interface 1. refer to section about can controller 1c00 h to 1cff h reserved for can interface 0. refer to section about can controller 1d00 h to 1dff h reserved for can interface 1. refer to section about can controller 1e00 h to 1eff h reserved
mb90590/590g series 27 (continued) note: initial value of _ represents unused bit; x represents unknown value. addresses in the rage 0000 h to 00ff h , which are not listed in the table, are reserved for the primary functions of the mcu. a read access to these reserved addresses results in reading x, and any write access should not be performed. address register abbreviation access peripheral initial value 1ff0 h program address detection register 0 (low-order) padr0 r/w address match detection function xxxxxxxx b 1ff1 h program address detection register 0 (middle-order) padr0 r/w xxxxxxxx b 1ff2 h program address detection register 0 (high-order) padr0 r/w xxxxxxxx b 1ff3 h program address detection register 1 (low-order) padr1 r/w xxxxxxxx b 1ff4 h program address detection register 1 (middle-order) padr1 r/w xxxxxxxx b 1ff5 h program address detection register 1 (high-order) padr1 r/w xxxxxxxx b 1ff6 h to 1fff h reserved
mb90590/590g series 28 n n n n can controllers the can controller has the following features: ? conforms to can specification version 2.0 part a and b - supports transmission/reception in standard frame and extended frame formats ? supports transmission of data frames by receiving remote frames ? 16 transmitting/receiving message buffers - 29-bit id and 8-byte data - multi-level message buffer configuration ? provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as 1d acceptance mask - two acceptance mask registers in either standard frame format or extended frame formats ? bit rate programmable from 10 kbit/s to 2 mbit/s (when input clock is at 16 mhz) list of control registers address register abbreviation access initial value can0 can1 000070 h 000080 h message buffer valid register bvalr r/w 00000000 00000000 b 000071 h 000081 h 000072 h 000082 h transmit request register treqr r/w 00000000 00000000 b 000073 h 000083 h 000074 h 000084 h transmit cancel register tcanr w 00000000 00000000 b 000075 h 000085 h 000076 h 000086 h transmit complete register tcr r/w 00000000 00000000 b 000077 h 000087 h 000078 h 000088 h receive complete register rcr r/w 00000000 00000000 b 000079 h 000089 h 00007a h 00008a h remote request receiving register rrtrr r/w 00000000 00000000 b 00007b h 00008b h 00007c h 00008c h receive overrun register rovrr r/w 00000000 00000000 b 00007d h 00008d h 00007e h 00008e h receive interrupt enable register rier r/w 00000000 00000000 b 00007f h 00008f h
mb90590/590g series 29 list of control registers address register abbreviation access initial value can0 can1 001c00 h 001d00 h control status register csr r/w, r 00---000 0----0-1 b 001c01 h 001d01 h 001c02 h 001d02 h last event indicator register leir r/w -------- 000-0000 b 001c03 h 001d03 h 001c04 h 001d04 h receive/transmit error counter rtec r 00000000 00000000 b 001c05 h 001d05 h 001c06 h 001d06 h bit timing register btr r/w -1111111 11111111 b 001c07 h 001d07 h 001c08 h 001d08 h ide register ider r/w xxxxxxxx xxxxxxxx b 001c09 h 001d09 h 001c0a h 001d0a h transmit rtr register trtrr r/w 00000000 00000000 b 001c0b h 001d0b h 001c0c h 001d0c h remote frame receive waiting register rfwtr r/w xxxxxxxx xxxxxxxx b 001c0d h 001d0d h 001c0e h 001d0e h transmit interrupt enable register tier r/w 00000000 00000000 b 001c0f h 001d0f h 001c10 h 001d10 h acceptance mask select register amsr r/w xxxxxxxx xxxxxxxx b 001c11 h 001d11 h 001c12 h 001d12 h xxxxxxxx xxxxxxxx b 001c13 h 001d13 h 001c14 h 001d14 h acceptance mask register 0 amr0 r/w xxxxxxxx xxxxxxxx b 001c15 h 001d15 h 001c16 h 001d16 h xxxxx--- xxxxxxxx b 001c17 h 001d17 h 001c18 h 001d18 h acceptance mask register 1 amr1 r/w xxxxxxxx xxxxxxxx b 001c19 h 001d19 h 001c1a h 001d1a h xxxxx--- xxxxxxxx b 001c1b h 001d1b h
mb90590/590g series 30 list of message buffers (id registers) (continued) address register abbreviation access initial value can0 can1 001a20 h 001b20 h id register 0 idr0 r/w xxxxxxxx xxxxxxxx b 001a21 h 001b21 h 001a22 h 001b22 h xxxxx--- xxxxxxxx b 001a23 h 001b23 h 001a24 h 001b24 h id register 1 idr1 r/w xxxxxxxx xxxxxxxx b 001a25 h 001b25 h 001a26 h 001b26 h xxxxx--- xxxxxxxx b 001a27 h 001b27 h 001a28 h 001b28 h id register 2 idr2 r/w xxxxxxxx xxxxxxxx b 001a29 h 001b29 h 001a2a h 001b2a h xxxxx--- xxxxxxxx b 001a2b h 001b2b h 001a2c h 001b2c h id register 3 idr3 r/w xxxxxxxx xxxxxxxx b 001a2d h 001b2d h 001a2e h 001b2e h xxxxx--- xxxxxxxx b 001a2f h 001b2f h 001a30 h 001b30 h id register 4 idr4 r/w xxxxxxxx xxxxxxxx b 001a31 h 001b31 h 001a32 h 001b32 h xxxxx--- xxxxxxxx b 001a33 h 001b33 h 001a34 h 001b34 h id register 5 idr5 r/w xxxxxxxx xxxxxxxx b 001a35 h 001b35 h 001a36 h 001b36 h xxxxx--- xxxxxxxx b 001a37 h 001b37 h 001a38 h 001b38 h id register 6 idr6 r/w xxxxxxxx xxxxxxxx b 001a39 h 001b39 h 001a3a h 001b3a h xxxxx--- xxxxxxxx b 001a3b h 001b3b h 001a3c h 001b3c h id register 7 idr7 r/w xxxxxxxx xxxxxxxx b 001a3d h 001b3d h 001a3e h 001b3e h xxxxx--- xxxxxxxx b 001a3f h 001b3f h
mb90590/590g series 31 (continued) address register abbreviation access initial value can0 can1 001a40 h 001b40 h id register 8 idr8 r/w xxxxxxxx xxxxxxxx b 001a41 h 001b41 h 001a42 h 001b42 h xxxxx--- xxxxxxxx b 001a43f h 001b43 h 001a44 h 001b44 h id register 9 idr9 r/w xxxxxxxx xxxxxxxx b 001a45 h 001b45 h 001a46 h 001b46 h xxxxx--- xxxxxxxx b 001a47 h 001b47 h 001a48 h 001b48 h id register 10 idr10 r/w xxxxxxxx xxxxxxxx b 001a49 h 001b49 h 001a4a h 001b4a h xxxxx--- xxxxxxxx b 001a4b h 001b4b h 001a4c h 001b4c h id register 11 idr11 r/w xxxxxxxx xxxxxxxx b 001a4d h 001b4d h 001a4e h 001b4e h xxxxx--- xxxxxxxx b 001a4f h 001b4f h 001a50 h 001b50 h id register 12 idr12 r/w xxxxxxxx xxxxxxxx b 001a51 h 001b51 h 001a52 h 001b52 h xxxxx--- xxxxxxxx b 001a53 h 001b53 h 001a54 h 001b54 h id register 13 idr13 r/w xxxxxxxx xxxxxxxx b 001a55 h 001b55 h 001a56 h 001b56 h xxxxx--- xxxxxxxx b 001a57 h 001b57 h 001a58 h 001b58 h id register 14 idr14 r/w xxxxxxxx xxxxxxxx b 001a59 h 001b59 h 001a5a h 001b5a h xxxxx--- xxxxxxxx b 001a5b h 001b5b h 001a5c h 001b5c h id register 15 idr15 r/w xxxxxxxx xxxxxxxx b 001a5d h 001b5d h 001a5e h 001b5e h xxxxx--- xxxxxxxx b 001a5f h 001b5f h
mb90590/590g series 32 list of message buffers (dlc registers and data registers) (continued) address register abbreviation access initial value can0 can1 001a60 h 001b60 h dlc register 0 dlcr0 r/w ----xxxx b 001a61 h 001b61 h 001a62 h 001b62 h dlc register 1 dlcr1 r/w ----xxxx b 001a63 h 001b63 h 001a64 h 001b64 h dlc register 2 dlcr2 r/w ----xxxx b 001a65 h 001b65 h 001a66 h 001b66 h dlc register 3 dlcr3 r/w ----xxxx b 001a67 h 001b67 h 001a68 h 001b68 h dlc register 4 dlcr4 r/w ----xxxx b 001a69 h 001b69 h 001a6a h 001b6a h dlc register 5 dlcr5 r/w ----xxxx b 001a6b h 001b6b h 001a6c h 001b6c h dlc register 6 dlcr6 r/w ----xxxx b 001a6d h 001b6d h 001a6e h 001b6e h dlc register 7 dlcr7 r/w ----xxxx b 001a6f h 001b6f h 001a70 h 001b70 h dlc register 8 dlcr8 r/w ----xxxx 001a71 h 001b71 h 001a72 h 001b72 h dlc register 9 dlcr9 r/w ----xxxx b 001a73 h 001b73 h 001a74 h 001b74 h dlc register 10 dlcr10 r/w ----xxxx b 001a75 h 001b75 h 001a76 h 001b76 h dlc register 11 dlcr11 r/w ----xxxx b 001a77 h 001b77 h 001a78 h 001b78 h dlc register 12 dlcr12 r/w ----xxxx b 001a79 h 001b79 h 001a7a h 001b7a h dlc register 13 dlcr13 r/w ----xxxx b 001a7b h 001b7b h 001a7c h 001b7c h dlc register 14 dlcr14 r/w ----xxxx b 001a7d h 001b7d h 001a7e h 001b7e h dlc register 15 dlcr15 r/w ----xxxx b 001a7f h 001b7f h 001a80 h to 001a87 h 001b80 h to 001b87 h data register 0 (8 bytes) dtr0 r/w xxxxxxxx b to xxxxxxxx b
mb90590/590g series 33 (continued) address register abbreviation access initial value can0 can1 001a88 h to 001a8f h 001b88 h to 001b8f h data register 1 (8 bytes) dtr1 r/w xxxxxxxx b to xxxxxxxx b 001a90 h to 001a97 h 001b90 h to 001b97 h data register 2 (8 bytes) dtr2 r/w xxxxxxxx b to xxxxxxxx b 001a98 h to 001a9f h 001b98 h to 001b9f h data register 3 (8 bytes) dtr3 r/w xxxxxxxx b to xxxxxxxx b 001aa0 h to 001aa7 h 001ba0 h to 001ba7 h data register 4 (8 bytes) dtr4 r/w xxxxxxxx b to xxxxxxxx b 001aa8 h to 001aaf h 001ba8 h to 001baf h data register 5 (8 bytes) dtr5 r/w xxxxxxxx b to xxxxxxxx b 001ab0 h to 001ab7 h 001bb0 h to 001bb7 h data register 6 (8 bytes) dtr6 r/w xxxxxxxx b to xxxxxxxx b 001ab8 h to 001abf h 001bb8 h to 001bbf h data register 7 (8 bytes) dtr7 r/w xxxxxxxx b to xxxxxxxx b 001ac0 h to 001ac7 h 001bc0 h to 001bc7 h data register 8 (8 bytes) dtr8 r/w xxxxxxxx b to xxxxxxxx b 001ac8 h to 001acf h 001bc8 h to 001bcf h data register 9 (8 bytes) dtr9 r/w xxxxxxxx b to xxxxxxxx b 001ad0 h to 001ad7 h 001bd0 h to 001bd7 h data register 10 (8 bytes) dtr10 r/w xxxxxxxx b to xxxxxxxx b 001ad8 h to 001adf h 001bd8 h to 001bdf h data register 11 (8 bytes) dtr11 r/w xxxxxxxx b to xxxxxxxx b 001ae0 h to 001ae7 h 001be0 h to 001be7 h data register 12 (8 bytes) dtr12 r/w xxxxxxxx b to xxxxxxxx b 001ae8 h to 001aef h 001be8 h to 001bef h data register 13 (8 bytes) dtr13 r/w xxxxxxxx b to xxxxxxxx b 001af0 h to 001af7 h 001bf0 h to 001bf7 h data register 14 (8 bytes) dtr14 r/w xxxxxxxx b to xxxxxxxx b 001af8 h to 001aff h 001bf8 h to 001bff h data register 15 (8 bytes) dtr15 r/w xxxxxxxx b to xxxxxxxx b
mb90590/590g series 34 n n n n interrupt map interrupt cause i 2 os clear interrupt vector interrupt control register number address number address reset n/a # 08 ffffdc h ?? int9 instruction n/a # 09 ffffd8 h ?? exception n/a # 10 ffffd4 h ?? time base timer n/a # 11 ffffd0 h icr00 0000b0 h external interrupt (int0 to int7) *1 # 12 ffffcc h can 0 rx n/a # 13 ffffc8 h icr01 0000b1 h can 0 tx/ns n/a # 14 ffffc4 h can 1 rx n/a # 15 ffffc0 h icr02 0000b2 h can 1 tx/ns n/a # 16 ffffbc h 8/16 bit ppg 0/1 n/a # 17 ffffb8 h icr03 0000b3 h 8/16 bit ppg 2/3 n/a # 18 ffffb4 h 8/16 bit ppg 4/5 n/a # 19 ffffb0 h icr04 0000b4 h 8/16 bit ppg 6/7 n/a # 20 ffffac h 8/16 bit ppg 8/9 n/a # 21 ffffa8 h icr05 0000b5 h 8/16 bit ppg a/b n/a # 22 ffffa4 h 16-bit reload timer 0 *1 # 23 ffffa0 h icr06 0000b6 h 16-bit reload timer 1 *1 # 24 ffff9c h input capture 0/1 *1 # 25 ffff98 h icr07 0000b7 h output compare 0/1 *1 # 26 ffff94 h input capture 2/3 *1 # 27 ffff90 h icr08 0000b8 h output compare 2/3 *1 # 28 ffff8c h input capture 4/5 *1 # 29 ffff88 h icr09 0000b9 h output compare 4/5 *1 # 30 ffff84 h 8/10 bit a/d converter *1 # 31 ffff80 h icr10 0000ba h i/o timer/watch timer n/a # 32 ffff7c h serial i/o *1 # 33 ffff78 h icr11 0000bb h sound generator n/a # 34 ffff74 h uart 0 rx *2 # 35 ffff70 h icr12 0000bc h uart 0 tx *1 # 36 ffff6c h uart 1 rx *2 # 37 ffff68 h icr13 0000bd h uart 1 tx *1 # 38 ffff64 h uart 2 rx *2 # 39 ffff60 h icr14 0000be h uart 2 tx *1 # 40 ffff5c h flash memory n/a # 41 ffff58 h icr15 0000bf h delayed interrupt n/a # 42 ffff54 h
mb90590/590g series 35 *1: the interrupt request flag is cleared by the i 2 os interrupt clear signal. *2: the interrupt request flag is cleared by the i 2 os interrupt clear signal. a stop request is available. n/a:the interrupt request flag is not cleared by the i 2 os interrupt clear signal. note: for a peripheral module with two interrupt for a single interrupt number, both interrupt request flags are cleared by the i 2 os interrupt clear signal. at the end of i 2 os, the i 2 os clear signal will be asserted for all the interrupt flags assigned to the same in- terrupt number. if one interrupt flag starts the i 2 os and in the meantime another interrupt flag is set by a hardware event, the later event is lost because the flag is cleared by the i 2 os clear signal caused by the first event. so it is recommended not to use the i 2 os for this interrupt number. if i 2 os is enabled, i 2 os is initiated when one of the two interrupt signals in the same interrupt control register (icr) is asserted. this means that different interrupt sources share the same i 2 os descriptor which should be unique for each interrupt source. for this reason, when one interrupt source uses the i 2 os, the other interrupt should be disabled.
mb90590/590g series 36 n n n n electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0 v) *1: av cc , avrl and avrl should not exceed v cc and avrl should not exceed avrh. *2: v i and v o should not exceed v cc + 0.3v. v i should not exceed the specified ratings. however if the maximum current to/from an input is limited by some means with external components, the i clamp rating supercedes the v i rating. *3: the maximum output current is a peak value for a corresponding pin. *4: average output current is an average current value observed for a 100 ms period for a corresponding pin. *5: total average current is an average current value observed for a 100 ms period for all corresponding pins. note: average output current = operating current operating efficiency warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min. max. power supply voltage v cc v ss - 0.3 v ss + 6.0 v av cc v ss - 0.3 v ss + 6.0 v v cc = av cc * 1 avrh, avrl v ss - 0.3 v ss + 6.0 v av cc 3 avrh/l, avrh 3 avrl * 1 dv cc v ss - 0.3 v ss + 6.0 v v cc 3 dv cc input voltage v i v ss - 0.3 v ss + 6.0 v * 2 output voltage v o v ss - 0.3 v ss + 6.0 v * 2 clamp current i clamp - 2.0 2.0 ma "l" level max. output current i ol1 15 ma normal output * 3 "l" level avg. output current i olav1 4 ma normal output, average value * 4 "l" level max. output current i ol2 40 ma high current output * 3 "l" level avg. output current i olav2 30 ma high current output, average value * 4 "l" level max. overall output current ? i ol1 100 ma total normal output "l" level max. overall output current ? i ol2 330 ma total high current output "l" level avg. overall output current ? i olav1 50 ma total normal output, average value * 5 "l" level avg. overall output current ? i olav2 250 ma total high current output, average value * 5 "h" level max. output current i oh1 C15 ma normal output * 3 "h" level avg. output current i ohav1 C4 ma normal output, average value * 4 "h" level max. output current i oh2 C40 ma high current output * 3 "h" level avg. output current i ohav2 C30 ma high current output, average value * 4 "h" level max. overall output current ? i oh1 -100 ma total normal output "h" level max. overall output current ? i oh2 -330 ma total high current output "h" level avg. overall output current ? i ohav1 -50 ma total normal output, average value * 5 "h" level avg. overall output current ? i ohav2 -250ma total high current output, average value * 5 power consumption p d 500 mw mb90f594a, mb90f591a, mb90f594g 400 mw mb90594, mb90591, mb90594g operating temperature t a C40 +85 c storage temperature t stg C55 +150 c
mb90590/590g series 37 2. recommended conditions (v ss = av ss = 0 v) *: use a ceramic capacitor or a capacitor with equivalent frequency characteristics. the smoothing capacitor to be connected to the v cc pin must have a capacitance value higher than c s . warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min. typ. max. power supply voltage v cc av cc 4.5 5.0 5.5 v under normal operation mb90v590a mb90v590g mb90f594a mb90f594g mb90594 mb90594g 3.0 5.5 v maintains ram data in stop mode 4.75 5.0 5.25 v under normal operation mb90f591a mb90591 3.0 5.25 v maintains ram data in stop mode input h voltage v ihs 0.8 v cc v cc +0.3 v cmos hysteresis input pin v ihm v cc C 0.3 v cc +0.3 v md input pin input l voltage v ils v ss C 0.3 0.6v cc v cmos hysteresis input pin v ilm v ss C 0.3 v ss + 0.3 v md input pin smooth capacitor c s 0.022 0.1 1.0 m f* operating temperature t a C40 +85 c c c s ? c pin connection diagram
mb90590/590g series 38 3. dc characteristics (mb90v590a, mb90f594a, mb90594, mb90v590g, mb90f594g, mb90594g: v cc = 5.0 v 10 %, v ss = av ss = 0v, t a = - 40 c to + 85 c) (mb90f591a, mb90591: v cc = 5.0 v 5 %, v ss = av ss = 0v, t a = - 40 c to + 85 c) *: current values are tentative and subject to change without notice according to improvements in the character- istics. the power supply current testing conditions are when using the external clock. parameter symbol pin name condition value unit remarks min. typ. max. output h voltage v oh1 normal output v cc = 4.5 v, i oh1 = C4.0 ma v cc C 0.5 v v oh2 high cur- rent output v cc = 4.5 v, i oh2 = C30.0 ma v cc C 0.5 v output l voltage v ol1 normal output v cc = 4.5 v, i ol1 = 4.0 ma 0.4v v ol2 high cur- rent output v cc = 4.5 v, i ol2 = 30.0 ma 0.5v input leak current i il v cc = 5.5 v, v ss < v i < v cc C5 5 m a analog in- put leak cur- rent i ial an0 to an7 v cc = 5.5 v, av ss < v i < av cc C1 1 m a power supply current * i cc v cc v cc = 5.0 v 10%, internal frequency: 16 mhz, at normal operation. 3760ma mb90594/594g 5080ma mb90f594a/f594g 5080ma mb90f591a 4560ma mb90591 i ccs v cc = 5.0 v 10%, internal frequency: 16 mhz, at sleep mode. 1320ma mb90594/594g 1523ma mb90f594a/f594g 1523ma mb90f591a 1523ma mb90591 i cts v cc = 5.0 v 1%, internal frequency: 2 mhz, at timer mode 0.30.6ma mb90594/594g 0.35 0.6 ma mb90f594a/f594g 0.35 0.6 ma mb90f591a 0.35 0.6 ma mb90591 i cch v cc = 5.0 v 10%, at stop mode, t a = 25 c 520 m a mb90594/594g 520 m a mb90f594a/f594g 520 m a mb90f591a 520 m a mb90591 input capacity c in other than c, av cc , av ss , avrh, avrl, v cc, v ss, dv cc , dv ss , p70 to p87 515pf p70 to p87 15 30 pf
mb90590/590g series 39 4. ac characteristics (1) clock timing (mb90v590a, mb90f594a, mb90594, mb90v590g, mb90f594g, mb90594g: v cc = 5.0 v 10 %, v ss = av ss = 0v, t a = - 40 c to + 85 c) (mb90f591a, mb90591: v cc = 5.0 v 5 %, v ss = av ss = 0v, t a = - 40 c to + 85 c) *: frequency deviation indicates the maximum frequency difference from the target frequency when using a multi- plied clock. example of oscillation circuit parameter symbol pin name value unit remarks min. typ. max. oscillation frequency f c x0, x1 3 5 mhz when using an oscillation circuit. 3 16 mhz when using an external clock. oscillation cycle time t cyl x0, x1 200 333 ns when using an oscillation circuit. 62.5 333 ns when using an external clock. frequency deviation with pll* d f5% input clock pulse width p wh , p wl x0 10 ns duty ratio is about 30 to 70%. input clock rise and fall time t cr , t cf x0 5 ns when using external clock machine clock frequency f cp 1.516mhz machine clock cycle time t cp 62.5 666 ns flash read cycle time t cycfl 2 t cp ns when flash is accessed by cpu + a c ent r al f r equen c y f o - a d f a fo ------ 100% = t cyl p wh t cf p wl t cr 0.8 v cc 0.2 v cc x0 ? clock timing x0 x1 r c1 c2
mb90590/590g series 40 ? guaranteed operation range guaranteed pll operation range (mb90f591a, mb90591) guaranteed operation range (mb90v590a, mb90f594a, mb90594, mb90v590g, mb90f594g, mb90594g) guaranteed operation range (mb90f591a, mb90591) guaranteed pll operation range (mb90v590a, mb90f594a, mb90594, mb90v590g, mb90f594g, mb90594g) 5.5 5.25 4.75 4.5 3.0 power supply voltage v cc (v) 1.5 8 16 machine clock f cp (mhz) 16 12 4 9 8 3 4 8 16 machine clock f cp (mhz) external clock f c (mhz)* ? external clock frequency and machine clock frequency 4 3 2 1 1/2 (pll off) *: when using the oscillation circuit, the maximum oscillation clock frequency is 5 mhz.
mb90590/590g series 41 (2) reset and hardware standby input (mb90v590a, mb90f594a, mb90594, mb90v590g, mb90f594g, mb90594g: v cc = 5.0 v 10 %, v ss = av ss = 0v, t a = - 40 c to + 85 c) (mb90f591a, mb90591: v cc = 5.0 v 5 %, v ss = av ss = 0v, t a = - 40 c to + 85 c) *1: t cp represents one cycle time of the machine clock. no reset can fully initialize the flash memory if it is performing the automatic algorithm. *2: oscillation time of oscillator is time that the amplitude reached the 90%. in the crystal oscillator, the oscillation time is between several ms to tens of ms. in far / ceramic oscillator, the oscillation time is between hundreds of m s to several ms. in the external clock, the oscillation time is 0 ms. parameter symbol pin name value unit remarks min. max. reset input time t rstl rst 16 t cp * 1 ns under normal operation oscillation time of oscillator* 2 + 16 t cp * 1 ms in stop mode hardware standby input time t hstl hst 16 t cp * 1 ns under normal operation oscillation time of oscillator* 2 + 16 t cp * 1 ms in stop mode 0.6 v cc rst hst t rstl , t hstl 0.6 v cc under normal operation t rstl , t hstl 0.6v cc 0.6v cc rst hst x0 16 t cp internal operation clock internal reset oscillation time of oscillator oscillation setting time instruction execution 90 % of amplitude in stop mode
mb90590/590g series 42 (3) power on reset (mb90v590a, mb90f594a, mb90594, mb90v590g, mb90f594g, mb90594g: v cc = 5.0 v 10 %, v ss = av ss = 0v, t a = - 40 c to + 85 c) (mb90f591a, mb90591: v cc = 5.0 v 5 %, v ss = av ss = 0v, t a = - 40 c to + 85 c) note v cc must be kept lower than 0.2 v before power-on. the above values are used for creating a power-on reset. some registers in the device are initialized only upon a power-on reset. to initialize these register, turn on the power supply using the above values. . parameter symbol pin name condition value unit remarks min. max. power on rise time t r v cc 0.05 30 ms power off time t off v cc 50 ms due to repetitive operation t r 3.5 v 0.2 v v cc 0.2 v 0.2 v t off sudden changes in the power supply voltage may cause a power-on reset. to change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. in this case, change the supply voltage with the pll clock not used. if the voltage drop is 1 v or fewer per second, however, you can use the pll clock. v cc v ss 3v ram data being held it is recommended to keep the rising speed of the supply voltage at 50 mv/ms or slower.
mb90590/590g series 43 (4) uart0/1/2, serial i/o (mb90v590a, mb90f594a, mb90594, mb90v590g, mb90f594g, mb90594g: v cc = 5.0 v 10 %, v ss = av ss = 0v, t a = - 40 c to + 85 c) (mb90f591a, mb90591: v cc = 5.0 v 5 %, v ss = av ss = 0v, t a = - 40 c to + 85 c) *: t cp is the machine cycle (unit: ns) notes: ac characteristic in clk synchronized mode. c l is load capacity value of pins when testing. parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc sck0 to sck3 internal clock opera- tion output pins are c l = 80 pf + 1 ttl. 8 t cp * ns sck t sot delay time t slov sck0 to sck3, sot0 to sot3 C80 80 ns valid sin t sck - t ivsh sck0 to sck3, sin0 to sin3 100 ns sck - t valid sin hold time t shix sck0 to sck3, sin0 to sin3 60 ns serial clock "h" pulse width t shsl sck0 to sck3 external clock oper- ation output pins are c l = 80 pf + 1 ttl. 4 t cp ns serial clock "l" pulse width t slsh sck0 to sck3 4 t cp ns sck t sot delay time t slov sck0 to sck3, sot0 to sot3 150 ns valid sin t sck - t ivsh sck0 to sck3, sin0 to sin3 60 ns sck - t valid sin hold time t shix sck0 to sck3, sin0 to sin3 60 ns sck 2.4 v t scyc 0.8 v sot 0.8 v 2.4 v 0.8 v t slov sin 0.6 v cc 0.8 v cc t ivsh 0.6 v cc 0.8 v cc t shix ? internal shift clock mode
mb90590/590g series 44 (5)timer input timing (mb90v590a, mb90f594a, mb90594, mb90v590g, mb90f594g, mb90594g: v cc = 5.0 v 10 %, v ss = av ss = 0v, t a = - 40 c to + 85 c) (mb90f591a, mb90591: v cc = 5.0 v 5 %, v ss = av ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name condition value unit remarks min. max. input pulse width t tiwh tin0 4 t cp ns under normal operation t tiwl in0 to in5 1 m s in stop mode sck 0.8 v cc t slsh 0.6 v cc sot 0.8 v 2.4 v t slov sin 0.6 v cc 0.8 v cc t ivsh 0.6 v cc 0.8 v cc t shix 0.8 v cc 0.6 v cc t shsl ? external shift clock mode 0.6 v cc 0.8 v cc t tiwh 0.6 v cc 0.8 v cc t tiwl ? timer input timing
mb90590/590g series 45 (6)trigger input timing (mb90v590a, mb90f594a, mb90594, mb90v590g, mb90f594g, mb90594g: v cc = 5.0 v 10 %, v ss = av ss = 0v, t a = - 40 c to + 85 c) (mb90f591a, mb90591: v cc = 5.0 v 5 %, v ss = av ss = 0v, t a = - 40 c to + 85 c) (7) slew rate high current outputs (mb90f591a, mb90591, mb90594g and mb90f594g only) (mb90f594g, mb90594g: v cc = 5.0 v 10 %, v ss = av ss = 0v, t a = - 40 c to + 85 c) (mb90f591a, mb90591: v cc = 5.0 v 5 %, v ss = av ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name condition value unit remarks min. max. input pulse width t trgh t trgl int0 to int7, adtg 5 t cp ns parameter symbol pin name condition value unit remarks min. max. output rise/fall time t r2 t f2 port p70 to p77, port p80 to p87 1540ns 0.6 v cc 0.8 v cc t trgh 0.6 v cc 0.8 v cc t trgl ? trigger input timing ? slew rate output timing v h v l t r2 v h v l t f2 v h = v ol2 + 0.1 (v oh2 - v ol2 ) v l = v ol2 + 0.9 (v oh2 - v ol2 )
mb90590/590g series 46 5. a/d converter (mb90v590a, mb90f594a, mb90594, mb90v590g, mb90f594g, mb90594g: v cc = av cc = 5.0 v 10 %, v ss = av ss = 0v, 3.0 v avr+ - avr-, t a = - 40 c to + 85 c) (mb90f591a, mb90591: v cc = av cc = 5.0 v 5 %, v ss = av ss = 0v, 3.0 v avr+ - avr-, t a = - 40 c to + 85 c) *: when not operating a/d converter, this is the current (v cc = av cc = avrh = 5.0 v) when the cpu is stopped. parameter symbol pin name value unit remarks min. typ. max. resolution 10 bit conversion error 5.0 lsb nonlinearity error 2.5 lsb differential linearity error 1.9 lsb zero transition voltage v ot an0 to an7 avrl C 3.5 avrl +0.5 avrl + 4.5 mv full scale transition voltage v fst an0 to an7 avrh C 6.5 avrh C1.5 avrh + 1.5 mv conversion time 352t cp ns sampling time 64t cp ns analog port input current i ain an0 to an7 -1 +1 m a analog input voltage range v ain an0 to an7 avrl avrh v reference voltage range avrh avrl + 2.7 av cc v avrl 0 avrh C 2.7 v power supply current i a av cc 5ma i ah av cc 5 m a* reference voltage current i r avrh 400 600 m a mb90594 mb90v590a mb90v590g mb90f594a mb90f594g mb90f591a 140 600 m a mb90594g mb90591 i rh avrh 5 m a* offset between input channels an0 to an7 4 lsb
mb90590/590g series 47 6. a/d converter glossary resolution: analog changes that are identifiable with the a/d converter linearity error: the deviation of the straight line connecting the zero transition point (00 0000 0000 ? 00 0000 0001) with the full-scale transition point (11 1111 1110 ? 11 1111 1111) from actual conversion characteristics differential linearity error: the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value total error: the total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. (continued) total error 3ff 3fe 3fd 004 003 002 001 analog input avrl avrh actual conversion value d i g i t a l o u t p u t v nt (measured value) 0.5 lsb actual conversion characteristics theoretical characteristics 0.5 lsb {1 lsb (n C 1) + 0.5 lsb} [v] avrh C avrl 1024 1 lsb = (theoretical value) v ot (theoretical value) = avrl + 0.5 lsb[v] v fst (theoretical value) = avrh C 1.5 lsb[v] total error for digital output n [lsb] v nt C {1 lsb (n C 1) + 0.5 lsb} 1 lsb = v nt : voltage at a transition of digital output from (n C 1) to n
mb90590/590g series 48 (continued) 7. notes on using a/d converter select the output impedance value for the external circuit of analog input according to the following conditions, : ? output impedance values of the external circuit of 15 k w or lower are recommended. ? when capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. when the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 m s @machine clock of 16 mhz). ?error the smaller the | avrh - avrl |, the greater the error would become relatively. linearity error 3ff 3fe 3fd 004 003 002 001 analog input avrl avrh analog input avrl avrh actual conversion characteristics v ot (measured value) v fst (measured value) actual conversion value v nt {1 lsb (n C 1)+ v ot } theoretical characteristics d i g i t a l o u t p u t d i g i t a l o u t p u t differential linearity error theoretical characteristics v (n + 1)t (measured value) actual conversion value v nt (measured value) actual conversion value linearity error of digital output n v ot: voltage at transition of digital output from 000 h to 001 h v fst : voltage at transition of digital output from 3fe h to 3ff h [lsb] v nt C {1 lsb (n C 1) + v ot } 1 lsb = [v] v fst C v ot 1022 = 1 lsb C 1 lsb [lsb] v (n + 1)t C v nt 1 lsb = differential linearity error of digital n n + 1 n n C 1 n C 2 (measured value) comparator analog input 30 pf max. 3.2 k w max. ? equipment of analog input circuit model note: listed values must be considered as standards.
mb90590/590g series 49 n n n n ordering information part number package remarks mb90594pf mb90591pf MB90594GPF mb90f594gpf mb90f594apf mb90f591apf 100-pin plastic qfp (fpt-100p-m06) mb90v590acr mb90v590gcr 256-pin ceramic pga (pga-256c-a01) for evaluation
mb90590/590g series 50 n n n n package dimension 100-pin plastic qfp (fpt-100p-m06) dimensions in mm (inches) c 2000 fujitsu limited f100008-3c-3 "a" "b" 0.53(.021)max 0.18(.007)max details of "a" part 0 10 details of "b" part 12.35(.486) ref 16.30?.40 (.642?016) 0.05(.002)min (stand off) 0.15?.05(.006?002) index 23.90?.40(.941?016) 20.00?.20(.787?008) 17.90?.40 14.00?.20 (.551?008) (.705?016) 0.13(.005) m 18.85(.742)ref 22.30?.40(.878?016) 1 30 31 50 51 80 81 100 0.25(.010) 0.30(.012) 0.65(.0256)typ 0.30?.10 (.012?004) lead no. 0.80?.20 (.031?008) 3.35(.132)max (mounting height) 0.10(.004)
mb90590/590g series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0101 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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